Method of manufacturing a surface mount package

ABSTRACT

The present invention provides a method and apparatus for fabricating densely stacked ball-grid-array packages into a three-dimensional multi-package array. Integrated circuit packages are stacked on one another to form a module. Lead carriers provide an external point of electrical connection to buried package leads. Lead carriers are formed with apertures that partially surround each lead and electrically and thermally couple conductive elements or traces in the lead carrier to each package lead. Optionally thin layers of thermally conductive adhesive located between the lead carrier and adjacent packages facilitates the transfer of heat between packages and to the lead carrier. Lead carriers may be formed of custom flexible circuits having multiple layers of conductive material separated by a substrate to provide accurate impedance control and providing high density signal trace routing and ball-grid array connection to a printed wiring board.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is a continuation-in-part of application Ser.No. 08/774,699, filed Dec. 26, 1996 and a Continuing ProsecutionApplication filed Feb. 11, 1998, which is a continuation of Ser. No.08/497,565, filed Jun. 30, 1995, now issued as U.S. Pat. No. 5,631,193,which is a continuation of application Ser. No. 07/990,334, filed Dec.11, 1992, now issued as U.S. Pat. No. 5,484,959.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] This invention relates to a high density, integrated circuitmodule, which includes a plurality of vertically or horizontally stackedindividual surface mount or ball-grid-array integrated circuit packages.

[0004] 2. Brief Description of the Related Technology

[0005] An example of a fabrication method and apparatus for high densitylead-on-package modules by laminating one or more lead frames tostandard integrated circuit packages is disclosed in U.S. Pat. No.5,484,959, assigned to the common assignee of the present invention andincorporated herein by reference. Other methods for providing highdensity, stacked modules are disclosed in U.S. Pat. Nos. 5,279,029,5,367,766, 5,455,740, 5,450,959 and 5,592,364, all of which are assignedto the common assignee of the present invention and incorporated hereinby reference. The general methods and apparatus disclosed in thereferenced patents can be applied to the fabrication of stackedconfigurations comprised of individual ball-grid-array or surface mountpackages. However, the characteristic lead orientation, lead shape andlead content of ball-grid-array or surface mount packages impose adifferent set of parameters not adequately provided for by prior methodsand assemblies.

SUMMARY OF THE INVENTION

[0006] The present invention provides a novel method and apparatus formanufacturing three-dimensional, high density, integrated circuitmodules from standard ball-grid-array or other surface mount integratedcircuit packages which provides improved space efficiency and heatdissipation. One way to increase space efficiency is to stack individualpackages. Generally speaking, higher density generates more localizedheat and thus increases the need for efficient heat dissipation.Improving the thermal transfer characteristics of the individualintegrated circuit packages results in better heat dissipation for themodule, and improves reliability and durability.

[0007] The present invention provides a novel method of fabricating athree-dimensional module formed of stacked and aligned surface mount orball-grid-array packages. Ball-Grid-Array (BGA) integrated circuitpackages typically have leads that extend from the bottom surface of arectangular solid resin casing in a two-dimensional grid pattern. Theexternal portion of each lead finished with a ball of solder. Packageleads provide electrical and thermal coupling to one or more integratedcircuit dies that are embedded within the protective casing. Typically,the protective casing completely surrounds the embedded die but, in someBGA packages, the protective casing does not cover the inactive topsurface of the die. Near-chip scale packages provide 1.0 mmcenter-to-center lead spacing. Chip scale packaging such as MICRO_BGA™have center-to-center lead spacing of 0.5 mm. Chip scale packagingoffers excellent electrical characteristics including low capacitanceand thermal design.

[0008] Connectivity to the leads of individual packages in a module isprovided by thin substantially planar lead carriers located betweenadjacent packages. Lead carriers are adhered to adjacent packages with athermally conductive but electrically insulating adhesive. A leadcarrier is comprised of elongated electrically and thermally conductiveelements formed in one or more thin planes of conductive material thatare separated by high-dielectric material. Typically, each conductiveelement has at least one aperture, adapted to receive and electricallycouple to an individual package ball and at least one interconnect leadthat extends away from the module to provide external circuitconnectivity to package leads. Preferably, the lead carriers are formedfrom custom flexible circuits commercially available from 3M™ or othermanufacturers. These well known flexible circuits are typicallycomprised of one or more thin layers of conductive material that are diecut and drilled to form ground planes, signal traces, pads andapertures. The conductive layers are typically embedded in and betweenelectrically-insulating, high-dielectric material such as polyamide,polyester or teflon which results in circuits that are flexible, havedense trace, and provide accurate impedance control.

[0009] The present invention utilizes standard manufactured packages toform the multi-package module. Such packages typically have ballirregularities or inconsistencies, particularly ball length and soldercoating variations. These variations make automated assembly problematicsince the tolerances necessary to accommodate variation in ball lengthand excess solder, for example, do not permit the packages to beassembled within the more stringent requirements for automated assemblyof the module. According to one aspect of the present invention, theleads of the ball-grid-array packages are scythed prior to assembly oras an automated step during the assembly. Scything is a method where ahot razor knife skims off a layer from the distal end of all the leadsof a ball-grid-array package, reducing random excess lead length andproviding a uniform, closely tolerant lead length. The step of scythingallows multiple packages to be added to the module prior to a finalheating step where the solder for all the packages is flowed. Thismethod also has the advantage of increasing the minimal tolerances forpositioning of ball-grid-array package on the lead carrier. Analternative method that may also be used to compensate for excess solderfrom the leads is to provide channels formed in the walls or edges ofeach aperture of the lead carrier that receives the ball so the excesssolder, when heated, flows into the channels A channel is a void area ina conductive element which merges into the void area of an aperture. Anedge of the channel is in close proximity to the package leads and thevoid area extends away from the leads. Channels take advantage of thesurface tension of molten solder which will pull molten solder away fromleads to fill the channel.

[0010] Another object of the present invention is to provide an assemblywhich effectively dissipates heat generated during normal operation.Efficient thermal management increases the operational life of themodule, and improves reliability by eliminating the effects of elevatedtemperature on the electrical characteristics of the integrated circuitand packaging. When packages are not stacked, heat from the embeddedintegrated circuits, generated through normal operation, is primarilydissipated by convection from the package's external surfaces to thesurrounding air. When modules are formed by stacking packages, theburied packages have reduced surface area exposed to the air. The use ofthermally conductive adhesive facilitates the transmission of heatbetween adjacent packages and is an effective method of taking advantageof the exposed surfaces for removing heat from buried packages.

[0011] In the module of the present invention, the package leads arethermally coupled to the lead carrier and provide a path for heat fromthe embedded integrated circuits. Thermally conductive adhesive alsofacilitates transfer of heat from packages to the lead carrier.

[0012] In applications where it is desirable to reduce the package andmodule height, or where package or module warping is a concern, eachpackage may be constructed using any of the various techniques describedin U.S. Pat. Nos. 5,369,056, 5,369,058 and 5,644,161, each of which isassigned to the common assignee of the present invention andincorporated herein by reference. These patents describe methods forconstructing thin, durable packages and modules with enhanced heatdissipation characteristics and minimal warpage.

[0013] A common application of a stacked configuration is memorymodules. Most of the leads of each package are electrically connected tocorresponding leads of adjacent packages. A method is required to selectthe individual memory package being read, written or refreshed. Onemethod is to provide a custom manufactured lead carrier for eachpackage. A more cost-effective method is to use a common lead carrierdesign with extra package interconnect leads which is then modified byclipping off or no-connecting selected interconnect leads to make eachlead carrier in a stacked configuration unique. Methods for connecting aunique bit of a data word per package and for uniquely addressing eachpackage in a stacked configuration are described in U.S. Pat. Nos.5,279,029 and 5,371,866, both which are assigned to the common assigneeof the present invention and incorporated herein by reference. While theapparatus and methods of the present invention are described herein withreference to standard, single-size packages, it will be appreciated bythose of ordinary skill in the art, that those methods and apparatus areequally applicable to multiple-die packages.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a cross-sectional view of two adjacent packages of amodule of the present invention;

[0015]FIG. 2 is a top planar view of a typical lead carrier of thepresent invention;

[0016]FIG. 3a illustrates the preferred embodiment for an aperture forconnection with a package lead of the present invention;

[0017]FIG. 3b illustrates an alternative embodiment of an aperture forconnection with a package lead of the present invention;

[0018]FIG. 4 illustrates a horizontally stacked module of the presentinvention;

[0019]FIG. 5 illustrates a vertically stacked module of the presentinvention;

[0020]FIG. 6 illustrates an alternative embodiment of a horizontallystacked module of the present invention; and

[0021]FIG. 7 illustrates an alternative embodiment of horizontallystacked module of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Other and further objects, features and advantages will beapparent from the following description of the preferred embodiments ofthe invention, given for the purpose of disclosure and taken inconjunction with the accompanying drawings.

[0023] The letter of a reference character containing numerics followedby a letter, either identifies the relative placement of the numericreference within a stacked module or it identifies a specificembodiment.

[0024] Referring now to FIG. 1, a typical ball-grid-array package 50 iscomprised of an integrated circuit 51 surrounded by an essentiallyrectangular solid resin casing 55. Package leads 52 extend from thebottom surface 54 of the casing in a two-dimensional grid patternproviding electrical and thermal coupling to one or more integratedcircuit die 51 that are embedded within the protective casing. Theexternal portion of each package lead 52 includes a coating of solderhaving a semi-spherical shape. Typically, the protective casing 55completely surrounds the embedded die but, in some ball-grid-arraypackages 50, the protective casing 55 does not cover the inactive topsurface 53 of the die. Near-chip scale packages 50 provide 1.0 mmcenter-to-center spacing between leads 52. Chip scale packaging such asMICRO_BGA™ have center-to-center lead spacing of 0.5 mm. Chip scalepackaging offers excellent electrical characteristics including lowcapacitance and thermal design.

[0025]FIGS. 4 through 7 show various specific embodiments of stackedmodule M of the present invention. The letter M designates the module Mformed of a plurality of ball-grid-array packages 50. Typically, thepackages 50 are aligned as shown in FIGS. 4, 5 and 7 where the bottomsurfaces 54 of each package 50 are facing the same direction.Alternately, the packages 50 may be aligned where one or more of thepackages 50 are inverted in relation to the other packages 50 as shownin FIG. 6. In this embodiment, the top package 50 d is inverted withrespect to the bottom package 50 e; the top surface 53 of the toppackage 50 d is in substantially full contact with the adhesive 70 onthe top surface 53 of the lower package 50 e.

[0026] A typical application of one aspect of the present invention isshown in FIG. 1 which illustrates a partial cross-section of any twoadjacent packages 50 that comprise a module M. The internals of package50 b are not shown for simplicity. FIG. 1 shows two packages 50 a and 50b mounted on opposite sides of a lead carrier 60 comprised of a singlethin copper plane. Interconnect leads 64 extend away from the module Mto provide external circuit connectivity to package leads 52 of the toppackage 50 a. External connectivity may be provided in differentconfigurations as described in detail below with reference to FIGS. 4-7.A typical layout of a single plane lead carrier 60 is shown in FIG. 2.The lead carrier 60 is made to be flexible for increased reliability andease of assembly. A lead carrier 60 can be comprised of elongatedconductive elements 65 formed from a thermally and electricallyconductive thin planer material such as beryllium copper alloy C3 havinga thickness of about 3 mils. Each conductive element 65 is defined toinclude a trace, interconnect pad, via and any other conductive featureof the lead carrier that are electrically coupled. Other preferredalloys for the lead-carrier-conductive elements 62 are full hard or hardcopper alloys (110 or 197) or olin copper alloy 1094. Preferably, thelead carrier 60 is formed from custom flexible circuits from 3M™ andother manufacturers. These well known flexible circuits are typicallycomprised of one or more thin (1.4 mils thick) layers of conductivematerial that are die cut and drilled to form apertures 66, groundplanes and conductive elements 65 which include traces, mounting padsand leads. The conductive layers typically are flanked by a thin(typically 1 to 11 mill thick) layer of electrically-insulating,high-dielectric materials such at polyamide, polyester or teflon whichresults in circuit composites that are flexible. The material andthickness of individual layers that comprise the lead carriers 60 aswell as spacing between conductive elements 65 and the width ofconductive elements 65 can be precisely controlled to provide a accurateand consistent impedance control in select conductive elements 65. Leadcarriers 60 formed from custom flexible-circuits can have vias forconnecting traces 65 located on different planes and conductive pads (orleads), with solder coating having footprints that are compatible withstandards for ball-grid array packages 50 for electrical and mechanicalcoupling to a printed wiring board 80.

[0027] Typically, each conductive element 65 in a lead carrier 60 has atleast one aperture 66, adapted to receive an individual package lead 52and at least one interconnect portion 64 that extends away from themodule to provide an external point of electrical connection to packageleads 52. Interconnect portions 64 preferably have a spring-likeresiliency for increased reliability. Apertures 66 have about the samediameter as a package lead 52 allowing each package lead 52 to extendthrough the aperture 66 and for the lead carrier 60 to have substantialcontact with the bottom surface 54 of a package 50. The application ofheat (about 175 degrees centigrade) that is sufficient to cause thesolder comprising the package leads 52 to flow will cause the solder toadhere to a thin area of a conductive element 65 on the surface of thelead carrier 60 facing away from the package 50 that surrounds eachaperture 66 to form flange 55 that provides excellent electrical andmechanical coupling between package leads 52 and the lead carrier 60.FIG. 3a illustrates the preferred semi-circle shape 66 a for theaperture 66 where the conductive element 65 partially surrounds thepackage ball 52. The semicircle shape 66 a, as opposed to a full-circleshape, enables an increased space for routing the conductive elements 65of the lead carrier 60.

[0028] The present invention utilizes standard manufactured packages 50to form the multi-package module M. Such packages 50 typically havepackage lead 52 irregularities or inconsistencies, particularly, leadlength and solder coating variations. These variations make automatedassembly problematic since the tolerances necessary to accommodatevariation in lead 52 length, for example, do not permit the packages 50to be assembled within the more stringent requirements for automatedassembly of the module M. The package leads 52 typically have excesssolder that can cause electrical shorts between package leads 52.According to one aspect of the present invention, the leads 52 of theball-grid-array packages 50 are scythed prior to assembly or as anautomated step during the assembly after the lead carrier 60 isattached. Scything is the preferred method of reducing the length bywhich package leads 52 extend from the package 50. Scything is a methodwhere a hot razor knife skims off the distal portion of all packageleads 52.

[0029] Referring again to FIG. 1, lead carriers 60 are adhered toadjacent packages 50 with a thermally conductive butelectrical-insulating adhesive 70. The adhesive 70 may be epoxy, such asRogers Corp. R/flex 8970 which is B-staged phenolic butyryl epoxy, thatmay be laminated at a temperature of 130 degrees centigrade and cured ata temperature of about 175 degrees centigrade. The preferred method isto use a 2 mil thick sandwich of polyamide film 70, such as Kapton™which includes a 0.5 mil thick layer of adhesive on both sides (athree-layer system). A thermally conductive filled adhesive 70 may beused to enhance the transfer of heat between adjacent packages 50, andbetween the packages 50 and carrier 60.

[0030] Referring now to FIG. 4, a horizontally oriented embodiment ofthe present invention is illustrated. Typically, a module M ispreassembled and then attached to a PWB 80 or other circuit carryingsubstrate. Alternately, the preassembled module M may be inserted intoan integrated circuit socket.

[0031] In FIG. 4, a plurality of integrated circuit packages 50, eachwith an attached lead carrier 65, are stacked in a horizontally-orientedmodule M. In this configuration, each lead carrier 65 has an externalinterconnect portion 64 which extends from both sides of the module M toprovide interconnection to an electrically and thermally conductiveexternal interconnect structure 40. Structure 40 provides mechanicalrigidity to the module M and is adhered to the upper surface 41 of theuppermost package 50. Structure 40 also includes circuit boardinterconnection portions 43 which may be formed for industry-standardsocketability with an electrical socket carried in circuit boardsubstrate 80.

[0032] A vertically-oriented configuration of module M is illustrated inFIG. 5. In this embodiment, lead carriers 60 are formed with externalinterconnect portions 64 all extending to one side which requires theconductive elements 65 to be more densely spaced. In this embodiment,external interconnect portions 64 are spaced in row and columnconfiguration for socketing or soldering to circuit connections oncircuit board substrate 80.

[0033] Another embodiment of module M is illustrated with reference toFIG. 6. In this embodiment, module M is formed in a two-high stackcomprised of packages 50 e and 50 d. In this embodiment, package 50 ehas its package leads 52 mounted directly to corresponding array ofexternal circuit connect pads carried in substrate 80. Upper package 50d is inverted with respect to package 50 e and mounted to package 50 dwith thermally conductive adhesive layer 70. Surface 54 of package 50 dincludes package leads 52. A lead carrier 60, formed as described above,is adhered to surface 54 of package 50 d with thermally conductiveadhesive 70 External circuit interconnect portions 64 provide electricalconnectivity for upper package 50 d to circuit connection pads carriedin substrate 80.

[0034] Referring now to FIG. 7, module M is shown in an alternativethree-high configuration comprised of individual packages 50 a, 50 b and50 c. A lead carrier 60 is adhered to the package lead surface 54 ofeach package. For clarity, package leads 52 are not shown as to packages50 a and 50 b. Lead carriers 60 for packages 50 a and 50 b includeexternal circuit connect portions 64 b which are formed to nest togetherto provide mechanical rigidity and electrical and thermal conductivityfor the module M. Lower package 50 c has lead carrier 60 c adhered toits lower surface 54 in the manner described above with thermallyconductivity, electrically insulating adhesive. In this embodiment,circuit connection portions 64 a of lead carrier 60 c are selectivelyinterconnected to connection portions 64 b. Package leads 52 of lowerpackage 50 c are connected to external circuit connections carried insubstrate 80 in a standard ball-grid-array pattern.

[0035] According to one specific method of the present invention, amethod for manufacture a module M involves the following steps: (1)mounting an adhesive 70 a to the bottom surface 56 of a package 50; (2)aligning and mounting a lead carrier 60 to the adhesive 70 whereinapertures 66 receive the package leads 52; (3) scything of the distalend of all package leads 52; (4) applying heat (about 175 degreescentigrade) to cure adhesive 70 and flow the package lead 52 soldercoating; (5) mounting a second thin layer of adhesive 70 b to the leadcarrier 60; and (6) mounting another package 50 to the adhesive 70 b,wherein the top surface 56 of the package 50 has substantial contactwith the adhesive. Steps 1 though 6 are repeated for each package 50added to the module, except steps 5 and 6 are not repeated for the lastpackage 50. For reliability and remanufacturability, it may be desirableto test each package 50 as it is added to the module M.

[0036] The preferred method replaces the steps of applying adhesive 70 aand 70 b with the preliminary step of applying double-sided adhesivetape 70 to both upper and lower surfaces of each lead carrier 60 priorto assembly. The step of applying heat to cause solder 53 to flow and tocure adhesive 66 after each step of mounting a package 50 is eliminatedif the leads 52 of the package 50 are reduced in height prior toassembly and a thin area of the second layer of adhesive 70 b aroundeach aperture 66 is left void to allow the package leads 52 to form aflange when heat is applied. The module M may be assembled using asuitably formed manufacturing jig provided to hold individual packages50 in alignment as they are stacked together with interspaced leadcarriers 60 and adhesive carrying tape 70. In this embodiment, theentire module M may be preassembled and a single heating event appliedto flow the solder and cure the adhesive 70 as pressure is exerted onthe module M to compress the layers.

[0037] Referring now to FIG. 3b, an alternative embodiment whichcompensates for excess solder steps utilizes channels 66 c formed ineach aperture 66 b. FIG. 3b illustrates one shape of an aperture 66 bwith multiple channels 66 c. A channel 66 c is a void area in aconductive element 65 which merges into the void area of an aperture 66.When a package lead 52 is inserted into the aperture 66 b, an edge ofeach channel 66 c is in close proximity to the package leads 52. Thevoid area of the channel 66 c extends away from the ball 52. When heatis applied such that the solder coating the package leads 52 becomesmolten, excess solder is pulled by the inherent surface tension ofmolten solder to fill the voided area.

[0038] Communication between individual integrated circuits embeddedwithin packages 50 and signals external to the modules are provided byvarious methods for implementing an external structure. Methods andapparatus of such structures are described in U.S. Pat. Nos. 5,279,029and 5,367,766. Alternatively, the external structure 40 may be formedintegral to the leads 64 extending from the lead carrier 61 as shown inFIGS. 6 and 7. In the embodiment shown in FIG. 7, the leads 64 b areformed such to electrically and thermally connect directly to selectedadjacent leads 64 b. Leads 64 may be formed with a substrate mountingportion 65 that may have a standard “gull-wing,” “J-lead” shape.

[0039] The foregoing disclosure and description of the invention areillustrative and explanatory of the preferred embodiments. Changes inthe size, shape, materials and individual components used, elements,connections and construction may be made without departing from thespirit of the invention.

What is claimed is:
 1. A method of manufacture of a high density,integrated circuit module of the type including surface mount integratedcircuit packages, comprising the steps of: (a) providing a plurality ofintegrated circuit packages wherein each said package has a bottomsurface and a top surface, and wherein a plurality of package leadsextend from each said bottom surface; (b) providing one or more leadcarriers, wherein each said lead carrier is comprised of a plurality ofelectrically and thermally conductive elements, each of said conductiveelements being formed having a lead connection portion adapted toreceive one of said package leads, and an interconnect portion thatprovides an external-to-module point of electrical connection to one ofsaid package leads; (c) mounting one of said lead carriers to saidbottom surface of one of said packages, wherein select ones of saidmounted package leads are received by select ones of said leadconnection portions; and (d) mounting another one of said packages tosaid lead carrier of step c, forming a multiple package module.
 2. Themethod of claim 1 for manufacture of an integrated circuit module,wherein each said conductive element of said lead carriers is formedhaving an aperture adapted to receive one of said leads.
 3. The methodof claim 1 for manufacture of an integrated circuit module, wherein eachsaid package lead is comprised of solder and further comprising the stepof: (a) applying heat, wherein said solder becomes molten and eachrespective said package lead is electrically coupled to an associatedsaid conductive element that provides an external-to-module point ofelectrical connection to a package lead.
 4. The method of claim 3 formanufacture of an integrated circuit module, further comprising the stepof: (a) repeating in order steps (c) and (d) of claim 1 , and step (a)of claim 3 for each additional package provided in step (a) of claim 1 ,wherein the package of the previous step (d) becomes the package of step(c).
 5. The method of claim 3 for manufacture of an integrated circuitmodule, further comprising prior to step (a) of claim 3 , the step of:(a) repeating in order steps (c) and (d) of claim 1 for each additionalpackage provided in step (a) of claim 1 , wherein the package of theprevious step (d) becomes the package of step (c).
 6. The method ofclaim 2 for manufacture of an integrated circuit module, furthercomprising prior to step (d) of claim 1 the step of: (a) reducing thelength of all said package leads by removing part of the distal end ofeach said package lead.
 7. The method of claim 6 for manufacture of anintegrated circuit module, wherein the method of reducing length of saidpackage leads is by scything.
 8. The method of claim 2 for manufactureof an integrated circuit module, wherein said apertures are formed witha channel adapted to fill with excess solder when said heat is applied.9. The method of claim 2 for manufacture of an integrated circuitmodule, wherein each said aperture is formed to have a semi-circularshape.
 10. The method of claim 1 , wherein the methods of mountinginclude the use of adhesive.
 11. The method of claim 10 , wherein saidadhesive is silicon adhesive tape.
 12. The method of claim 10 , whereinsaid adhesive is thermally conductive.
 13. The method of claim 10 ,wherein said adhesive is B-staged adhesive.
 14. The method of claim 1 ,wherein one of said lead carrier includes a substrate mounting portion,and further comprising the steps of: (a) providing a substrate adaptedto receive said substrate mounting portions; and (b) mounting saidstacked multiple package module to said substrate.
 15. The method ofclaim 14 , wherein said substrate has conductive pads, and wherein saidsubstrate mounting portion has a plurality of solder coated leadsadapted to electrically connect with said substrate conductive pads. 16.The method of claim 1 , wherein said lead carrier is formed to have aplurality of thin layers of conductive material cut to form electricallyisolated conductive elements, and wherein said plurality of thin layersof conductive material are separated by thin layers of dielectricmaterial.
 17. The method of claim 16 , wherein the material, thethickness of said layers, the spacing between said conductive elements,and the geometry of said lead carriers are selected to obtain a desiredimpedance in select said conductive elements.
 18. The method of claim 1, further comprising the steps of: (a) mounting one or more externalstructures having one or more electrically and thermally conductivestructure elements, wherein each said conductive structure element isadapted to be received by one of said interconnect portions; and (b)electrically and thermally connecting select ones of said conductivestructure elements to select ones of said interconnect portions.
 19. Themethod of claim 1 , wherein at least one of said interconnect portionsis adapted to connect to said interconnect portion of an adjacent leadcarrier, and further comprising the steps of: (a) electrically couplingselect said interconnect portions to select interconnect portions ofsaid adjacent lead carriers.
 20. The method of claim 1 , wherein a firstof said lead carriers is dissimilar to a second of said lead carriers,wherein one said interconnect portions of said first lead carrier andthe corresponding interconnect portions of said second lead carrier donot electrically connect to corresponding said package leads.
 21. Themethod of claim 1 , further comprising prior to step c the step of: (a)rendering electrically inactive a selected one of said interconnectportions by opening the electrical signal path in select one of saidconductive elements.
 22. The method of claim 1 , wherein a select one ofsaid interconnect portions of one of said lead carriers is removed. 23.The method of claim 20 , wherein said lead carriers provide a uniqueaddress for each said package.
 24. The method of claim 20 , wherein saidlead carriers provides a unique, data word bit position for each saidpackage.
 25. A method of manufacture of a high density, integratedcircuit module, of the type including surface mount integrated circuitpackages, comprising the steps of: (a) providing a first and a secondintegrated circuit package, wherein each said package has a bottomsurface and a top surface, wherein a plurality of package leads extendfrom each said bottom surface; (b) providing at least one lead carrier,wherein said lead carrier is comprised of a plurality of electricallyand thermally conductive elements, each of said conductive elements isformed having a package lead connection portion adapted to receive oneof said package leads and an interconnect portion that provides anexternal-to-module point of electrical connection to one of said packageleads; (c) mounting said second package to said surface of said firstpackage, wherein said top surface of said second package is orientatedin the direction of said first package; and (d) mounting said leadcarrier to the bottom surface of said second package, wherein saidpackage leads of said second package are received by select ones of saidpackage lead connection portions forming a stacked, multiple packagemodule.
 26. The method of claim 25 for manufacture of an integratedcircuit module wherein each said lead connection portion is formedhaving an aperture adapted to receive one of said package leads.
 27. Themethod of claim 25 , wherein the methods of mounting include the use ofadhesive.
 28. The method of claim 25 , wherein at least one of saidinterconnect portions includes a substrate mounting portion, and furthercomprising the steps of: (a) providing a substrate adapted to receivesaid substrate mounting portions; and (b) mounting said stacked multiplepackage module.
 29. A high density, integrated circuit module of thetype including a surface mount integrated circuit packages comprising: aplurality of an integrated circuit packages, wherein each said packagehas a bottom surface and a top surface and, wherein a plurality ofpackage leads extend from said bottom surface; a lead carrier comprisedof a plurality of electrically and thermally conductive elements,wherein each of said conductive elements is formed having a leadconnection portion adapted to receive one of said package leads, and aninterconnect portion that provides an external-to-module point ofelectrical connection to one of said package leads; and said packagesand said lead carrier are aligned and stacked on the other to form amodule, wherein two adjacent of said packages flank one of said leadcarriers, wherein select ones of said package leads of one of saidadjacent packages are received by select ones of said lead connectportions of said lead carrier.
 30. The integrated circuit module ofclaim 29 , wherein each said lead connection portion is formed having anaperture adapted to receive one of said package leads.
 31. Theintegrated circuit module of claim 30 , wherein each said aperture isformed to have a semi-circular shape.
 32. The integrated circuit moduleof claim 30 , wherein each said aperture is formed to include peripheralchannels adapted to fill with excess molten solder.
 33. The integratedcircuit module of claim 29 , further comprising a first and secondadhesive layer, wherein said first adhesive layer is located betweensaid lead carrier and one of said adjacent packages, and the said secondadhesive layer is located between said lead carrier and the other ofsaid adjacent packages.
 34. The integrated circuit module of claim 33 ,wherein said adhesive is thermally conductive.
 35. The integratedcircuit module of claim 29 , further comprising: a substrate-mountingportion formed integral to the distal end of one said interconnectportion; and a substrate attached to said substrate-mounting portions.36. The integrated circuit module of claim 29 , further comprised of:one or more electrically and thermally conductive external structureseach having a substrate mounting portion; and wherein select ones ofsaid external structures are electrically and thermally coupled toselect ones of said interconnect portions.
 37. The integrated circuitmodule of claim 29 , wherein a first of said lead carriers of saidmultiple package module is dissimilar to a second of said lead carriersof said multiple package module, wherein one of said interconnect leadsof said first lead carrier and the corresponding interconnect portionsof said second lead carrier do not electrically connect to correspondingsaid package leads.
 38. The integrated circuit module of claim 30 ,wherein a select one of said interconnect portions is renderedelectrically inactive by opening the electrical signal path in selectone of said conductive elements.
 39. The integrated circuit module ofclaim 30 , wherein a select one of said interconnect portions isremoved.
 40. The integrated circuit module of claim 38 , wherein saidlead carriers provide a unique address for each said package.
 41. Theintegrated circuit module of claim 38 , wherein said lead carriersprovide a unique data word bit position for each said package.